I have a matrix inversion circuit coded in VHDL targeted on a Xilinx Virtex-2 6000. I'm using currently 32 bits floating point arithmetic with parametrisable fraction length. The algorithm that originated the circuit contains a series of loops, so in hardware I use the same circuit and I have a state machine that deals with the loops. The main operation in the loop is a subtraction. This causes the values to keep getting smaller after each loop.

The input data being scaled between 1 and -1, the successive subtractions result in the final values being too small to be represented with the precision I chose. I don't want to add more bits because that would take too much space. A multiplication of two complex numbers requires 4 multiplication of integers and Xilinx's dedicated multipliers being limited to 18-bits, my representation of signed numbers by 32-bits words already takes twice the number of multipliers. More than 32 bits will be way too much.

My question is this: do you know how to deal with real-time precision handling? I need a scheme to either downscale or upscale my data so that it stays within the bounds of my word precision. I've never done this before and it's been stumping me for months. I kept putting it off, but now it's all I've got left to do.

Thanks for your help.